There are many commercially successful non-volatile memory products being used today, particularly in the form of small form factor cards, which employ flash EEPROM (Electrically Erasable and Programmable Read Only Memory) cells formed on one or more integrated circuit devices. A memory controller, usually, but not necessarily, on a separate integrated circuit device interfaces with a host to which the card is removably connected and controls operation of the non-volatile memory within the card. Such a controller typically includes a microprocessor, some non-volatile read-only-memory (ROM), a volatile random-access-memory (RAM) and one or more special circuits such as one that calculates an error-correction-code (ECC) from data that passes through the controller during the programming and reading operations. Some of the commercially available card formats include CompactFlash (CF) cards, MultiMedia cards (MMC), Secure Digital (SD) cards, personnel tags (P-Tag), and Memory Stick cards. Hosts include personal computers, notebook computers, personal digital assistants (PDAs), various data communication devices, digital cameras, cellular telephones, portable audio players, automobile sound systems, and similar types of equipment. In some systems, a removable card does not include a controller and the host controls operation of the memory in the card. Examples of this type of memory system include Smart Media cards and xD cards. Thus, control of the memory may be achieved by software on a controller in the card or by control software in the host. Besides a memory card implementation, this type of memory can alternatively be embedded into various types of host systems. In both removable and embedded applications, host data may be stored in the memory according to a storage scheme implemented by memory control software.
Two general memory cell architectures have found commercial application, NOR and NAND. In a typical NOR architecture, memory cells are connected between adjacent bit line source and drain diffusions that extend in a column direction with control gates connected to word lines extending along rows of cells. A memory cell includes at least one storage element positioned over at least a portion of the cell channel region between the source and drain. A programmed level of charge on the storage elements thus controls an operating characteristic of the cells, which can then be read by applying appropriate voltages to the addressed memory cells. Examples of such cells, their uses in memory systems, and methods of manufacturing them are given in U.S. Pat. Nos. 5,070,032, 5,095,344, 5,313,421, 5,315,541, 5,343,063, 5,661,053 and 6,222,762. These patents, along with all other patents and patent applications referenced in this application are hereby incorporated by reference in their entirety.
A typical NAND architecture utilizes strings of more than two series-connected memory cells, such as 16 or 32, connected along with one or more select transistors between individual bit lines and a reference potential to form columns of cells. Word lines extend across cells within many of these columns. An individual cell within a column is read and verified during programming by causing the remaining cells in the string to be turned on so that the current flowing through a string is dependent upon the level of charge stored in the addressed cell. Examples of NAND architectures and their operation as part of a memory system are found in U.S. Pat. No. 6,522,580.
For purposes of this application, the block is the erase unit, a minimum number of cells that are simultaneously erasable. Each block typically contains one or more pages of data, the page being the minimum unit of programming and reading. Each page typically stores one or more sectors of data, the size of the sector being defined by the host system.
The charge storage elements of flash EEPROM cells, as discussed in the foregoing referenced patents, are most commonly electrically conductive floating gates, typically formed from conductively doped polysilicon material. An alternate type of memory cell useful in flash EEPROM systems utilizes a non-conductive dielectric material in place of the conductive floating gate to store charge in a non-volatile manner. A triple layer dielectric formed of silicon oxide, silicon nitride and silicon oxide (ONO) is sandwiched between a conductive control gate and a surface of a semi-conductive substrate above the memory cell channel. The cell is programmed by injecting electrons from the cell channel into the nitride, where they are trapped and stored in a limited region, and erased by injecting hot holes into the nitride. Examples of specific cell structures and architectures employing dielectric storage elements and are described in U.S. Pat. No. 6,925,007.
As in many integrated circuit applications, the pressure to shrink the silicon substrate area needed to implement some integrated circuit function also is present in flash EEPROM memory cell architectures. It may be desirable to increase the amount of digital data that can be stored in a given area of a silicon substrate, in order to increase the storage capacity of a given size memory card or other types of packages for a non-volatile memory, or to both increase capacity and decrease size. One way to increase the storage density of data is to store more than one bit of data per memory cell and/or per storage unit or element. This is accomplished by dividing storage element's charge level voltage range into more than two windows, in order to create more than two states. The use of four such states, for example, allows each cell to store two bits of data. Similarly, eight states may store three bits of data per storage element. Multiple state flash EEPROM structures using floating gates and their operation are described in U.S. Pat. Nos. 5,043,940 and 5,172,338, and structures using such dielectric floating gates are described in U.S. Pat. No. 6,925,007. Selected portions of a multi-state memory cell design may also be operated in two states (binary) for various reasons, in a manner described in U.S. Pat. Nos. 5,930,167 and 6,456,528.
Individual flash EEPROM cells may store an amount of charge in a charge storage element or unit that is representative of one or more bits of data. The charge level of a storage element controls the threshold voltage (commonly referenced as VT) of its memory cell, which is used as a basis of reading the storage state of the cell. A threshold voltage window may be divided into a number of ranges, one for each of the two or more storage states of the memory cell. These ranges may be separated by guardbands that include a nominal sensing level that allows determining the storage states of the individual cells. These storage levels may shift as a result of disturbances in the stored charge caused by programming, reading, or erasing operations performed in neighboring or other related memory cells, pages, or blocks. Error correction codes (ECCs) are therefore typically calculated by the controller and stored along with the host data being programmed and used during reading to verify the data and perform some level of data correction if necessary. Also, shifting charge levels can be restored back to the centers of their state ranges from time-to-time, before disturbing operations cause them to shift completely out of their defined ranges and thus cause erroneous data to be read. This process, termed data refresh or read scrub, is described in U.S. Pat. Nos. 5,532,962 and 5,909,449. A read scrub operation may entail reading data in areas of a memory that may have received exposure to potentially disturbing signals, determining if the read data has been disturbed, and performing some corrective action on the disturbed read data. Disturbed data may be detected by verifying ECCs associated with the data to be tested. Disturbed data may be corrected by rewriting the data in the same location, or in a different location. Read scrubbing may be performed in a scheduled, continuous manner, throughout the memory, as described in U.S. Pat. No. 7,153,852.
The responsiveness of flash memory cells typically changes over time as a function of the number of times the cells are erased and re-programmed. This may be the result of the accumulation of small amounts of trapped in a storage element dielectric layer during each erase and/or re-programming operation. This generally results in the memory cells becoming less reliable, and may need higher voltages for erasing and programming as the memory cells age. The effective threshold voltage window over which the memory states may be programmed can also decrease as a result of this charge retention. This is described, for example, in U.S. Pat. No. 5,268,870. The result is a limited effective lifetime of the memory cells; that is, memory cell blocks may be subjected to only a preset number of erasing and re-programming cycles before they are mapped out of the system. The number of cycles to which a flash memory block is desirably subjected may depend upon the particular structure of the memory cells, the amount of the threshold window that is used for the storage states, the extent of the threshold window usually increasing as the number of storage states of each cell is increased. Depending upon these and other factors, the number of lifetime cycles can be as low as 10,000 and as high as 100,000 or even several hundred thousand.
Continual erasing and re-programming of data sectors in a relatively few logical block addresses may occur where the host continually updates certain sectors of housekeeping data stored in the memory, such as file allocation tables (FATs) and the like. Specific applications can also cause a few logical blocks to be re-written much more frequently than others with user data. For example, in response to receiving a command from the host to write data to a specified logical block address, the data are written to one of a few blocks of a pool of erased blocks. That is, instead of re-writing the data in the same physical block where the original data of the same logical block address resides, the logical block address is remapped into a block of the erased block pool. The block containing the original and now invalid data is then erased either immediately or as part of a later garbage collection operation, and then placed into the erased block pool. The result, when data in only a few logical block addresses are being updated much more than other blocks, is that a relatively few physical blocks of the system are cycled with the higher rate.
System control and directory data, such as file allocation tables (FATs) are produced, accessed, and updated in order to complete some memory read and write operations. Conventionally, this type of data is set up in the controller RAM, thereby allowing direct access by the controller. After the memory device is powered up, a process of initialization enables the flash memory to be scanned in order to compile the necessary system control and directory information to be placed in the controller RAM. If the size of the controller RAM is insufficient to store all of the system control and directory data, a portion of system control and directory data may be stored in the non-volatile memory.
In some memories, a page may consist of a portion of a block that can hold multiple sectors of data. Once the page has been written, no further writing may be possible without corrupting the data that is already written. For memories using such a system, a page may be defined by a set of memory cells that are connected to the same word line. Such memories may be inefficiently programmed where data is received in amounts that are less than the size of a page. For example, where data is received one sector at a time, just one sector may be programmed to a page. No additional data may be programmed to the page without risk of corrupting the sector of data that is already saved there. In another example, when small amounts of data are received with delay between portions of data, each portion may be written to a separate page of the memory, where a portion may need less than a page of storage.